The present invention relates to computer systems and, more particularly, to computer systems with built-in test hardware. A major objective of the present invention is to improve testability of complex computer systems.
Much of modern progress is associated with advances in computer technology. Computer performance has roughly doubled every eighteen months for over a decade, and the best estimates are that this pace will be sustained for years to come. Most of the performance increases have been due to improvements in semiconductor manufacturing technology, which have allowed microprocessors and memory to be built with smaller circuit elements and faster speeds.
In addition, developments in parallel processing, microprocessor architecture, and memory architecture have also contributed significantly to the performance increases. Increasing numbers of computers use multiple processors to permit parallel processing to exceed the performance limits imposed on von Neuman architecture (one-instruction-at-a-time) machines. Modern microprocessors include multiple execution units, permitting parallelism within single processors. Memory architectures have provided multi-level memory systems in which relatively large-but-slow memory holds the bulk of the data and the instructions used by a microprocessor, while relatively small-but-fast cache memory holds frequently used memory items.
Both microprocessor architecture and memory architecture have evolved to yield the now typical two-level cache architecture: a relatively small-but-fast level-1 (L1) cache is built into the microprocessor, while a relatively large-but-slow level-2 (L2) cache is external to the microprocessor. (The L2 cache is still smaller and faster than main memory.)
A typical modern high-performance computer can include multiple microprocessors, each with an internal L1 cache and an associated L2 cache. The microprocessors communicate with each other, with main memory, and with peripherals over a communications bus. The communications bus has an associated communications protocol. Associated with each microprocessor is a processor-to-memory-bus interface (more commonly referred to as a "processor-to-memory interface" or "PMI") that translates between the microprocessor protocol and the bus protocol. Conveniently, the interface can also serve as a L2 cache manager.
Testing is a major concern for computer manufacturers. Testing is used to assist computer design and development, to ensure quality of manufactured units before shipping, and to help diagnose problem units. Many computer problems arise only under very specific circumstances, which may be hard to determine. The number of possible computer states that should be considered in a test increases dramatically according to the complexity and number of microprocessors in a system. One of the challenges of testing is to test event combinations that include rare events such as error conditions and interruptions.
Many computers include hardware that permits indications of normally rare events to be generated under the control of a test program while the system is in a test mode. Depending on the test hardware provided, the event indications can be simple or complex to generate. In either case, it is not practical to generate the test program code to adequately test a sufficient fraction of possible event combinations for development, quality assurance, and diagnostic purposes. Furthermore, running such a comprehensive test program can be very time consuming.
To the extent that some rare events are more difficult to generate than other events, a test program might favor testing the latter. More generally, all test programs reflect some presumptions as to what event combinations must be tested and which can be omitted. A test program can be designed so that test parameters can be entered by a tester, but such flexibility adds another level of complexity to the testing program.
To simplify test programs and their development and to increase the rate at which testing occurs, what is needed is a system that allows more testing to be done in a shorter time with less test program code. Preferably, such a system would facilitate testing of event combinations with at least some rare events.